Integrated circuit devices using self-aligned shallow trench isolation technology may provide a reduced number of fabrication steps during manufacture of the integrated circuit device, enhanced reliability of a gate oxide layer and/or narrower threshold voltage distribution in a cell array. Accordingly, to improve performance of conventional flash memory devices, self-aligned shallow trench isolation technology has been applied to highly integrated flash memory devices typically requiring low fabrication costs and high reliability.
FIGS. 1 through 4 illustrate aspects of conventional flash memory devices. FIG. 1 is a top plan view illustrating conventional flash memory devices, FIGS. 2 and 3 are cross-sectional views illustrating conventional flash memory devices, taken along lines A–A′ and B–B′ of FIG. 1, respectively.
Referring now to FIGS. 1 through 3, a plurality of device isolation patterns are provided on an integrated circuit substrate 2 to define a plurality of active regions. A control gate electrode 16 crosses over the device isolation patterns. A floating gate pattern 9 is disposed between the control gate electrode 16 and the active regions. As illustrated in FIG. 2, the flash memory device further includes a trench oxide layer 6, an insulating pattern 14 and an intergate dielectric pattern 13.
The device isolation pattern includes the trench oxide layer 6 and the insulating pattern 14. The trench oxide layer 6 is provided on sidewalls of a trench region provided in the integrated circuit substrate. The insulating pattern 14 is provided in the trench region. The floating gate pattern 9 includes a lower gate pattern 4a and an upper gate pattern 8. The lower gate pattern 4a is provided between the device isolation patterns, and the upper gate pattern 8 is provided on the lower gate pattern 4a. A portion of the upper gate pattern 8 may extend on a surface of the device isolation pattern. The intergate dielectric pattern 13 is disposed between the control gate electrode 16 and the floating gate pattern 9. The intergate dielectric pattern 13 typically includes first 10, second 11 and third 12 layers of silicon oxide, silicon nitride and silicon oxide, respectively. The control gate electrode 16 typically includes first and second layers, for example, a polysilicon layer 14 on the intergate dielectric pattern 13 and a metal silicide layer 15 on the polysilicon layer 14.
As further illustrated in FIG. 3, the flash memory device further includes a tunnel insulating pattern 3 and source/drain regions S/D. The tunnel insulating pattern 3 is provided between the floating gate pattern 9 and the integrated circuit substrate 2. The source/drain regions S/D are provided in the integrated circuit substrate 2 adjacent to the floating gate pattern 9 to be aligned to sidewalls of the floating gate pattern 9. Referring again to FIG. 2, conventional flash memory devices may include a bird's beak 7 (thickening of the trench oxide layer 6) at the edge of the tunnel insulating pattern 3 adjacent to the trench oxide layer 6.
Referring now to FIG. 4, methods of forming conventional devices include forming the tunnel insulating pattern 3, a lower conductive pattern 4 and a hard mask pattern 5 on the integrated circuit substrate 2. A trench may be formed on the integrated circuit substrate and may be aligned to sidewalls of the hard mask pattern 5. A thermal oxidization process may be applied to the integrated circuit substrate 2 including having the trench to form the trench oxide layer 6 on sidewalls and a bottom of the trench. The sidewalls of the lower conductive pattern 4 may be oxidized resulting in the bird's beak 7 at the edge of the tunnel insulating pattern 3 caused by an oxygen atom diffused through an interface of the tunnel insulating pattern 3 and the lower conductive pattern 4.
Referring again to FIG. 3, the flash memory device includes a gate sidewall oxide layer 19 on the sidewalls of the control gate electrode 16 and the floating gate pattern 9. The gate sidewall oxide layer 19 may reduce the amount of etch damage of the sidewalls of the control gate electrode 16 and the floating gate pattern 9. According to conventional methods of fabrication, during formation of the gate sidewall oxide layer 19, oxygen atoms may be diffused through an interface of the intergate dielectric pattern 13 to oxidize the control gate electrode 16 and the floating gate pattern 9. Accordingly, the silicon oxide layer at the edge 18 of the intergate dielectric pattern 13 may become thicker (form a bird's beak) relative to the other portions of the intergate dielectric pattern 13. Furthermore, the oxygen atom may be diffused through the interface of the tunnel insulating pattern 3 adjacent to the source/drain regions S/D. Thus, the edge 17 of the tunnel insulating pattern adjacent to the source/drain region S/D may also become thicker (form a bird's beak).
The presence of the bird's beak on the tunnel insulating pattern and the intergate dielectric pattern may cause the reliability of the flash memory device to deteriorate and may cause an increase in the distribution of the threshold voltage in the cell array. In particular, the presence of the bird's beak on the intergate dielectric pattern may lower a coupling ratio of the flash memory device, an erase speed of the flash memory device and a write speed of the flash memory device.